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The DLX713X, 5x7 Dot Matrix Intelligent Display(R) Device Appnote 25
This application note is intended to serve as a design and application guide for users of the DLO7135 and DLG7137 OSRAM Intelligent Displays. This appnote covers device electrical description, operation, general circuit design considerations and interfacing to microprocessors. Electrical Description The DLX713X intelligent alphanumeric 5x7 dot matrix display contains memory, character generator, multiplexing circuits, and drivers built into a single package. Figure 1 is a block diagram of the DLX713X. The unit consists of 35 LED die arranged in a 5x7 pattern and a single CMOS integrated circuit chip. The IC chip contains the column drivers, row drivers, 128 character generator ROM, memory, multiplex and blanking circuitry. Figure 1. DLX713X block diagram Package Thirty-five dots form a 0.48 x 0.68 inch overall character size in a 0.700 x 0.800 inch dual-in-line package. The 50 degree wide viewing angle complements the large display and is the ideal display for industrial control applications. Display construction is filled reflector type with the intregrated circuit in the back also filled with IC-grade epoxy. This results in a very rugged part which is resistant to moisture, shock, and vibration. Figure 2. Physical dimensions in inches (mm)
.018 (.45) sq. Pin 1 Indicator Device Marking Begins Over Pin 1 .075 (1.91) ref. .800 (20.32) 1.00 (2.54) typ. EIA Date Code .125 (3.18) Luminous Intensity Code .100 (2.54) typ. .700 (17.78) DLO7135 Z .50 (12.70) ref. .48 (12.19) .080 (2.03) diam. ref.
DLO7135 SIEMENS YYWW
1.00 (2.54) typ.
.68 (17.27)
D0 D1 D2 D3 D4 D5 D6
Z
RoW Driver
Character ROM
Memory
.160 (4.06)
.295 (7.49) .325 (8.26)
.150 (3.81)
WR CE
Multiplex Circuitry
Column Driver
.050 (1.27)
.600 (15.24)
BL0 BL1 L1
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
1
May 31, 2000-13
Table 1. Electrical inputs Pin 1 2 3 4 5 6 7 Name VCC LT lamp test CE chip enable WR write BL1 brightness BL0 brightness GND Pin 14 13 12 11 10 9 8 Name D6 data input (MSD) D5 data input D4 data input
Figure 3. Character set
D0 D1 D2 D3 D6 D5 D4 HEX ASCII CODE 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F
0
0
1
1
D3 data input D2 data input D1 data input D0 data input (LSD)
0 1 0 2
0
1
1
3
1
0
0
4
Table 2. Pin description VCC GND D0-D6 CE Positive Supply +5 V Ground
1
0
1
5
1
1
0
6
1
1
1
7
Data Lines, see Figure 3 (Character set) Chip Enable (active low) Determines which device in an array will accept data Write (active low) Data and chip enable must be present and stable before and after the write pulse (see DLX713X data sheet for timing) Blanking Control Input (active low) Used to control level of display brightness Lamp Test (active low) Causes all dots to light at 1/2 brightness
D0-D6 T DS
1. High=1 level. 2. Low=0 level.
Figure 4. Timing characteristics
WR TW T CES CE
WR
BL0, BL1 LT
TDH
Operation In a dot matrix display system, it is advantageous to use a multiplexed approach with 12 drivers (5 digit plus 7 segments) rather than 35 segment drivers, reducing the number of drives and interconnections required. A multiplexed system must be a synchronous system or the digits or elements may have different on (lit) times and therefore varying brightness. The DLX713X is an internally multiplexed display but the data entry is asynchronous. Loading data is similar to writing into a RAM. Present the data, select the chip, and give a write signal. For a multidigit system, each digit has its own unique location and will display its contents until replaced by another code. The waveforms of Figure 4 demonstrates the relationship of the signals required to generate a write cycle. Check the data sheet for minimum values required for each signal.
Display Blanking and Dimming The DLX713X Intelligent Display has the capability of three levels of brightness plus blank. Figure 5 shows the combination of BL0 and BL1 for the different levels of brightness. The BL0 and BL1 inputs are independent of write and chip enable and does not affect the contents of the internal memory. A flashing display can be achieved by pulsing the blanking pins at a 1-2 hertz rate. Either BL0 or BL1 should be held high to light up the display. Table 3. Dimming and blanking control Brightness Level Blank 1/7 brightness 1/2 brightness full brightness BL1 0 0 1 1 BL0 0 1 0 1
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Appnote 25
2
May 31, 2000-13
Lamp Test The lamp test when activated causes all dots on the display to be illuminated at 1/7 brightness. It does not destroy any previously stored characters. The lamp test function is independent of chip enable, write, and the settings of the blanking inputs. This convenient test gives a visual indication that all dots are functioning properly. Because lamp test does not affect the display memory, it can be used as a cursor or pointer in a line of displays. General Design Considerations When using the DLX713X on a separate display board having more than six inches of cable length, it may be necessary to buffer all of the input lines. A non-inverting 74LS244 buffer can be used. The object is to prevent transient current into the DLX713X protection diodes. The buffers should be located on the display board and as close to the displays as possible. Because of high switching currents caused by the multiplexing, local power supply bypass capacitors are also needed in many cases. These should be 10 volt, tantalum type having 10 uf capacitance. The capacitors may only be required every 2 displays depending on the line regulation and other noise generators. Decoupling capacitors should also be used across VCC and ground of each display. Typical value of these capacitors is 0.01 mF/ 10 V. If small wire cables are used it is good engineering practice to calculate the wire resistance of the ground and the +5 volt wires. More than 0.2 volt drop (at 100 ma per digit) should be avoided, since this loss is in addition to any inaccuracies or load regulation of the power supply. The 5 volt power supply for the DLX713X should be the same one supplying the VCC to all logic devices. If a separate supply must be used then local buffers should be used on all the inputs and these buffers should be powered from the display power supply. This precaution is to avoid line transients or any logic signals to be higher than VCC during power up.
Interfacing For an eight digit display using the DLX713X, interfacing to a single chip microprocessor is easy and straight forward. Figure 5. Block diagram of the Intel 8031 controller
DO
x x x x x
D7
BLO BL1 LT WR CE
BUFFER
P3.0 P3.1 P3.2 P3.6
74LS244
8031
PO
8 8 3 8 A0-A7
8 ALE PSEN
LATCH
OE
DECODER
EPROM 27xx
Conclusion Note that although other manufacturers' products are used in the examples, this application note does not imply specific endorsement, or warranty of other manufacturers' products by OSRAM. The interface schemes shown demonstrate the simplicity of using the DLX713X dot matrix Intelligent Display. Slight timing differences may be encountered for various microprocessors, but can be resolved similar to those encountered when using different RAM's. The techniques used in the examples were shown for their generality. The user will undoubtedly invent other schemes to optimize his particular system to its requirements.
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
74LS138
74373
3
May 31, 2000-13
BLO BL1 LT WR CE
Appnote 25
Program Listing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ; BY DAN WATSON ; TO DO LAMP TEST,SET 100% BRIGHTNESS ; AND WRITE `SIEMENS*' ; P3.0 = BLO\ ; P3.1 = BL1\ ; P3.2 = LT\ ; P3.6 = WR\ ; RO = DIGIT ADDRESS ( CHIP ENABLES - CE\ ) ; R1 = DIGIT COUNTER ; R7 = R6 = R5 = WAIT REGISTERS 0000 0000 0003 0006 0009 000C 000F 0010 0011 0013 0015 0017 001A 001B 001C 001D 001E 001F 0021 0022 0024 0024 0024 0026 0027 0029 002A 002C 002D 002F 0030 0032 0033 0035 0036 0037 003C 003F 003F .ORG 00H INIT:JMP BEGIN BEGIN:CALL WAIT1 MOV P3,#00H CALL WAIT1 MOV P3,#07H NOP NOP MOV R0,#00H MOV R1,#08H MOV A,#00H MOV DPTR,#TEXT WRT:MOVC A,@A+DPTR MOVX @R0,A INC DPTR INC R0 CLR A DJNZ R1,WRT GO:NOP JMP GO
02 12 75 12 75 00 00 78 79 74 90 93 F2 A3 08 E4 D9 00 01
00 00 B0 00 B0
03 24 00 24 07
; ; ; ;
DELAY FOR uC TO STABILIZE LAMP TEST DISPLAY LT\ FOR A WHILE SET ALL 8 DISPLAYS TO 100% BRT
00 08 00 00 37
; ; ; ; ; ; ; ;
DIGIT 7 ADDRESS 8 DIGIT COUNTER CLEAR ACC. ADDRESS OF THE MESSAGE LOAD FIRST CHAR. INTO THE ACC. DIGIT ADDRESS AND DATA WRITE NEXT CHARACTER ADDRESS NEXT DIGIT (6) ADDRESS
F9 21
; WRITE ALL 8 CHAR. ; MESSAGE ALWAYS ON
7F 88 00 7E FF 00 7D FF 00 DD FE 00 DE F8 00 DF F2 00 22 53 49 45 4D 45 4E 53 2A .END
WAIT1:MOV R7,#88H NOP WAIT2:MOV R6,#FFH NOP WAIT3:MOV R5,#FFH NOP DJNZ R5,$ NOP DJNZ R6,WAIT3 NOP DJNZ R7,WAIT2 NOP RET TEXT:DB `SIEMENS*'
; DELAY LOOPS
2000 Infineon Technologies Corp. * Optoelectronics Division * San Jose, CA www.infineon.com/opto * 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG * Regensburg, Germany www.osram-os.com * +49-941-202-7178
Appnote 25
4
May 31, 2000-13

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